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1 ?2017 integrated device technology, inc. may 31, 2017 description the 8t49n240 is a fractional-feedback single channel jitter attenuator with frequency translation. it is equipped with three integer and one fractional output dividers, allowing the generation of up to four different output frequencies, ranging from 8khz to 867mhz. these frequencies are completely independent of the input reference frequencies and the crystal reference frequency. the outputs may select among lvpecl, lvds, hcsl, or lvcmos output levels. the 8t49n240 accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input. the internal pll can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer. the pll can use the second input for redundant backup of the primary input reference, but in this case, both input clock references must be integer related in frequency. the device supports hitless reference switching between input clocks. the device monitors both input clocks for loss of signal (los), and generates an alarm when an input clock failure is detected. automatic and manual hitless reference switching options are supported. los behavior can be set to support gapped or un-gapped clocks. the 8t49n240 supports holdover. the holdover has an initial accuracy of 50ppb from the point where the loss of all applicable input reference(s) has been detected. it maintains a historical average operating point for the pll that may be returned to in holdover at a limited phase slope. the pll has a register-selectable loop bandwidth from 0.2hz to 6.4khz. the device supports output enable and clock select inputs and lock, holdover, and los status outputs. the device is programmable through an i 2 c interface. it also supports i 2 c master capability to allow the register configuration to be read from an external eeprom. factory pre-programmed devices are also available using the on-chip one time prog rammable (otp) memory. typical applications ? otn, including itu-t g.709 (2009) fec ? cpri interfaces ? fiber optics ? 40g/100g ethernet ? gb ethernet, terabit ip switches / routers features ? four differential outputs ? excellent jitter performance: ? <200fs (typical) rms (including spurs): 12khz to 20mhz for integer-divider outputs in jitter attenuator mode or in fractional-feedback synthesizer mode ? operating modes: synthesizer, jitter attenuator ? operates from a 10mhz to 54mhz fundamental-mode crystal ? initial holdover accuracy of + 50ppb ? accepts up to two lvpecl, lvds, lvhstl, or lvcmos input clocks ? accepts frequencies ranging from 8khz to 875mhz ? auto and manual clock selection with hitless switching ? clock input monitoring including support for gapped clocks ? phase-slope limiting and fully hitless switching options to control output clock phase transients ? three outputs generate lvpecl / lvds / hcsl clocks, one output generates lvpecl / lvds / hcsl / lvcmos clocks ? output frequencies ranging from 8khz up to 867mhz (differential) ? output frequencies ranging from 8khz to 250mhz (lvcmos) ? three integer dividers with fixed divider ratios (see table 3 ) ? one fractional output divider ? programmable loop bandwidth settings from 0.2hz to 6.4khz ? optional fast-lock function ? four general purpose i/o pins with optional support for status and control: ? two output enable control inputs provide control over the four clocks ? manual clock selection control input ? lock, holdover, and loss-of-signal alarm outputs ? open-drain interrupt pin ? register programmable through i 2 c or via external i 2 c eeprom ? full 2.5v or 3.3v supply modes, with some support for 1.8v ? -40c to 85c ambient operating temperature ? package: 6 x 6 x 0.9 mm 40-vfqfn, lead-free (rohs 6) 8t49n240 datasheet femtoclock ? ng ultra-performance jitter attenuator
2 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet block diagram figure 1. block diagram s_a
3 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet pin assignments figure 2. pin assignments for 6mm x 6mm 40-lead vfqfn package pin descriptions table 1. pin descriptions [a] number name type description 1v cca power analog function supply for core analog functions. 2.5v or 3.3v supported. 2v cca power analog function supply for analog functions associated with pll. 2.5v or 3.3v supported. 3 gpio[0] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 4v cco0 power high-speed output supply for output pair q0, nq0. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 5 q0 o universal output clock 0. for more information, see output drivers . 6 nq0 o universal output clock 0. for more information, see output drivers . 7 gpio[1] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 8 nq1 o universal output clock 1. for more information, see output drivers . 9 q1 o universal output clock 1. for more information, see output drivers . 10 v cco1 power high-speed output supply for output pair q1, nq1. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 11 sdata i/o pullup i 2 c interface bi-directional data. 12 sclk i/o pullup i 2 c interface bi-directional clock. 8t49n240 q2 q3 v cco3 v cco2 nq2 gpio[2] nq3 gpio[3] nint v cca gpio[0] v cco0 q0 v cca v cca nq0 gpio[1] nq1 q1 v cco1 osco v cca osci v cccs s_a1 cap1 cap2 cap_ref v cca nrst 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 12345678910 11 12 13 14 15 16 17 18 19 20 clk0 v cc v ee sclk sdata v cc nclk0 clk1 nclk1 s_a0
4 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet 13 v cc power core digital function supply. 2.5v or 3.3v supported. 14 epad v ee power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. 15 v cc power core digital function supply. 2.5v or 3.3v supported. 16 clk0 i pulldown non-inverting differential clock input 0. 17 nclk0 i pullup / pulldown inverting differential clock input 0. v cc / 2 when left floating (set by internal pullup / pulldown resistors) 18 clk1 i pulldown non-inverting differential clock input 1. 19 nclk1 i pullup / pulldown inverting differential clock input 1. v cc / 2 when left floating (set by internal pullup / pulldown resistors) 20 s_a0 i pulldown i 2 c address bit a0. 21 v cco2 power high-speed output supply voltage for output pair q2, nq2. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 22 q2 o universal output clock 2. for more information, see output drivers . 23 nq2 o universal output clock 2. for more information, see output drivers . 24 gpio[2] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 25 nq3 o universal output clock 3. for more information, see output drivers . 26 q3 o universal output clock 3. for more information, see output drivers . 27 v cco3 power high-speed output supply voltage for output pair q3, nq3. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 28 gpio[3] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 29 nint o open-drain with pullup interrupt output. 30 v cca power analog function supply for analog functions associated with pll. 2.5v or 3.3v supported. 31 nrst i pullup master reset input> lvttl / lvcmos interface levels: 0 = all registers and state machines are reset to their default values 1 = device runs normally 32 v cca power analog function supply for core analog functions. 2.5v or 3.3v supported. 33 osci i crystal input. accepts a 10mhz - 54mhz reference from a clock oscillator or a 12pf fundamental mode, parallel-resonant crystal. 34 osco o crystal output. this pin should be connected to a crystal. if an oscillator is connected to osci, then this pin must be left unconnected. 35 s_a1 i pulldown i 2 c address bit a1. 36 v cccs power output supply for control and status pins: gpio[3:0], sdata, sclk, s_a0, nint, nrst,s_a1 1.8v, 2.5v or 3.3v supported. table 1. pin descriptions [a] (cont.) number name type description
5 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet 37 cap1 analog pll external capacitance. 38 cap2 analog pll external capacitance. 39 cap_ref analog external capacitance for input reference clock circuitry. 40 v cca power analog function supply for analog functions associated with pll. 2.5v or 3.3v supported. [a] pullup and pulldown refer to internal input resistors. see table 2 , pin characteristics, for typical values. table 2. pin characteristics, v cc = v ccox [a] = 3.3v5% or 2.5v5% [a] v ccox denotes: v cco0, v cco1, v cco2 or v cco3. symbol parameter test conditions minimum typical maximum units c in input capacitance [b] [b] this specification does not apply to the osci or osco pins. 3.5 pf r pullup input pullup resistor sdata, sclk, nrst, gpio[3:0] 51 k ? r pulldown input pulldown resistor s_a0, s_a1 51 k ? c pd power dissipation capacitance (per output pair) q3, lvcmos v ccox = 3.465v 13 pf v ccox = 2.625v 15 pf v ccox = 1.89v 15 pf lvds, hcsl or lvpecl q[0:2] 2.5 pf q3, lvds, hcsl or lvpecl 4.5 pf r out output impedance gpio[3:0] v cccs = 3.3v 26 ? v cccs = 2.5v 32 v cccs = 1.8v 39 lvcmos q3, nq3 v ccox = 3.3v 18 ? v ccox = 2.5v 18 v ccox = 1.8v 24 table 1. pin descriptions [a] (cont.) number name type description
6 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet principles of operation the 8t49n240 can be locked to either of the input clocks and generate a wide range of synchronized output clocks. it could be u sed for example in either the transmit or receive path of synchronous ethernet equipment. the 8t49n240 accepts up to two differential or single-ended input clocks ranging from 8khz up to 875mhz. it generates up to fou r output clocks ranging from 8khz up to 867mhz. the pll path within the 8t49n240 supports three states: lock, holdover and free-run. lock and holdover status may be monitored on register bits and pins. the pll also supports automatic and manual hitless reference switching. in the locked state, the pll lo cks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accuracy of the input clock. in the ho ldover state, the pll will output a clock which is based on the selected holdover behavior. the pll within the 8t49n240 has an initial holdover frequency offset of 50ppb. in the free-run state, the pll outputs a clock with the same frequency accuracy as the external cry stal. upon power up, the pll will enter free-run state, in this state it generates output clocks with the same frequency accuracy as the external crystal. the 8t49n240 continuously monitors each input for activity (signal transitions). if no input references are p rovided, the device will remain locked to the crystal in free-run state and will generate output frequencies as a synthesizer. when an input clock has been validated the pll will transition to the lock state. in automatic reference switching, if the sele cted input clock fails and there are no other valid input clocks, the pll will quickly detect that and go into holdover. in the holdover s tate, the pll will output a clock which is based on the selected holdover behavior. if the selected input clock fails and another input clock is available then the 8t49n240 will hitlessly switch to that input clock. the reference switch can be either revertive or non-revertive. man ual switchover is also available with switchover only occurring on user command, either via register bit or via the clock select in put function of the gpio[3:0] pins. the device supports conversion of any input frequencies to four different output frequencies: one independent output frequency on q3 and three more integer-related frequencies on q[0:2]. the 8t49n240 has a programmable loop bandwidth from 0.2hz to 6.4khz. the device monitors all input clocks and generates an alarm when an input clock failure is detected. the device is programmable through an i 2 c and may also autonomously read its register settings from an internal one-time programmable (otp) memory or an external serial i 2 c eeprom. crystal input the crystal input on the 8t49n240 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of 10mhz - 54mhz the oscillator input also supports being driven by a single-ended crystal oscillator or reference clock. the initial holdover frequency offset is set by the device, but the long term drift depends on the quality of the crystal or os cillator attached to this port. bypass path the crystal input, clk0 or clk1 may be used directly as a clock source for the q[3] output divider. this may only be done for i nput frequencies of 250mhz or less.
7 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet input clock selection the 8t49n240 accepts up to two input clocks with frequencies ranging from 8khz up to 875mhz. each input can accept lvpecl, lvds , lvhstl, hcsl or lvcmos inputs using 1.8v, 2.5v or 3.3v logic levels. in manual mode, only one of the inputs may be chosen and if that input fails that pll will enter holdover. manual mode may be operated by directly selecting the desired input reference in the refsel register field. it may also operate via pin-selection of the desired input clock by selecting that mode in the refsel register field. in that case, gpio[2] must be use d as a clock select input (csel). csel = 0 will select the clk0 input and csel = 1 will select the clk1 input. in addition, the crystal frequency may be passed directly to the output divider q[3] for use as a reference. inputs do not support transmission of spread-spectrum clocking sources. since this family is intended for high-performance appl ications, it will assume input reference sources to have stabilities of + 100ppm or better, except where gapped clock inputs are used. if the pll is working in automatic mode, then one of the input reference sources is assigned as the higher priority. at power-u p or if the currently selected input reference fails, the pll will switch to the highest priority input reference that is valid at that tim e (see input clock monitor section for details). automatic mode has two sub-options: revertive or non-revertive. in revertive mode, the pll will switch to a reference with a hi gher priority setting whenever one becomes valid. in non-revertive mode the pll remains with the currently selected source as long as it rema ins valid. the clock input selection is based on the input clock priority set by the clock input priority control bit. input clock monitor each clock input is monitored for loss of signal (los). if no activity has been detected on the clock input within a user-selec table time period then the clock input is considered to be failed and an internal loss-of-signal status flag is set, which may cause an in put switchover depending on other settings. the user-selectable time period has sufficient range to allow a gapped clock missing ma ny consecutive edges to be considered a valid input. user-selection of the clock monitor time-period is based on a counter driven by a monitor clock. the monitor clock is fixed at the frequency of the pll?s vco divided by 8. with a vco range of 2.44ghz - 2.6ghz, the monitor clock has a frequency range of 305mh z to 325mhz. the monitor logic for each input reference will count the number of monitor clock edges indicated in the appropriate monitor co ntrol register. if an edge is received on the input reference being monitored, then the count resets and begins again. if the target edge count is reached before an input reference edge is received, then an internal soft alarm is raised and the count re-starts. during the s oft alarm period, the pll tracking will not be adjusted. if an input reference edge is received before the count expires for the second t ime, then the soft alarm status is cleared and the pll will resume adjustments. if the count expires again without any input reference edge b eing received, then a loss-of-signal alarm is declared. it is expected that for normal (non-gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer than the nominal period of that input reference. a margin of 2-3 monitor clock periods should give a reasonably quick re action time and yet prevent false alarms. for gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest ex pected clock gap period. the monitor count registers support 17-bit count values, which will support at least a gap length of two cloc k periods for any supported input reference frequency, with longer gaps being supported for faster input reference frequencies. since gapped clocks usually occur on input reference frequencies above 100mhz, gap lengths of thousands of periods can be supported. using this configuration for a gapped clock, the pll will continue to adjust while the normally expected gap is present, but wi ll freeze once the expected gap length has been exceeded and alarm after twice the normal gap length has passed. once a los on any of the input clocks is detected, the appropriate internal los alarm will be asserted and it will remain asser ted until that input clock returns and is validated. validation occurs once 8 rising edges have been received on that input reference. if another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation per iod starts over.
8 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet each los flag may also be reflected on one of the gpio[2:1] outputs. changes in status of any reference can also generate an in terrupt if not masked. holdover 8t49n240 supports a small initial holdover frequency offset in non-gapped clock mode. when the input clock monitor is set to su pport gapped clock operation, this initial holdover frequency offset is indeterminate since the desired behavior with gapped clocks i s for the pll to continue to adjust itself even if clock edges are missing. in gapped clock mode, the pll will not enter holdover until the i nput is missing for two los monitor periods. the holdover performance characteristics of a clock are referred as its accuracy and stability, and are characterized in terms of the fractional frequency offset. the 8t49n240 can only control the initial frequency accuracy. longer-term accuracy and stability a re determined by the accuracy and stability of the external oscillator. when the pll loses all valid input references, it will enter the holdover state. in fast average mode, the pll will initially m aintain its most recent frequency offset setting and then transition at a rate dictated by its selected phase-slope limit setting to a frequency offset setting that is based on historical settings. this behavior is intended to compensate for any frequency drift that may have occurred on the input reference before it was detected to be lost. the historical holdover value will have three options: ? return to center of tuning range within the vco band. ? instantaneous mode - the holdover frequency will use the dpll current frequency 100msec before it entered holdover. the accurac y is shown in the ac characteristics table, table 36 . ? fast average mode - an internal iir (infinite impulse response) filter is employed to get the frequency offset. the iir filter gives a 3db attenuation point corresponding to nominal a period of 20 minutes. the accuracy is shown in the ac characteristics table, table 36 . when entering holdover, the pll will set a separate internal hold alarm internally. this alarm may be read from internal status register, appear on the appropriate gpio pin and/or assert the nint output. while the pll is in holdover, its frequency offset is now relative to the crystal input and so the output clocks will be tracin g their accuracy to the local oscillator or crystal. at some point in time, depending on the stability and accuracy of that source, the clock(s) will have drifted outside of the limits of the holdover state and be considered to be in a free-run state. since this borderline is defined outsi de the pll and dictated by the accuracy and stability of the external local crystal or oscillator, the 8t49n240 cannot know or influence when that transition occurs. input to output clock frequency the 8t49n240 is designed to accept any frequency within its input range and generate four different output frequencies that are integer-related to the pll frequency and hence to each other, but not to the input frequencies. the internal architecture of th e device ensures that most translations will result in the exact output frequency specified. please contact idt for configuration softwa re or other assistance in determining if a desired configuration will be supported exactly. synthesizer mode operation the device may act as a frequency synthesizer with the pll generating its operating frequency from just the crystal input. by s etting the syn_mode register bit and setting the state[1:0] field to free-run, no input clock references are required to generate the desi red output frequencies. when operating as a synthesizer, the precision of the output frequency will be < 20ppb for any supported configuration. loop filter and bandwidth the 8t49n240 uses two external capacitors of fixed value to support its loop bandwidth. when operating in synthesizer mode a fi xed loop bandwidth of approximately 200khz is provided. when not operating as a synthesizer, the 8t49n240 will support a range of loop bandwidths: 0.2hz, 0.4hz, 0.8hz, 1.6hz, 3.2hz, 6 .4hz, 12hz, 25hz, 50hz, 100hz, 200hz, 400hz, 800hz, 1.6khz or 6.4khz.
9 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet the device supports two different loop bandwidth settings: acquisition and locked. these loop bandwidths are selected from the list of options described above. if enabled, the acquisition bandwidth is used while lock is being acquired to allow the pll to `fast-l ock'. once locked the pll will use the locked bandwidth setting. if the acquisition bandwidth setting is not used, the pll will use the lo cked bandwidth setting at all times. integer output divide rs (q0, q1 or q2) each integer output divider block (q0, q1 or q2) allows one of several fixed divide ratios to be chosen. odd divide ratios of 3 or 5, along with all even divide ratios from 4 to 160 are supported for each output. there is an independent divider block for each output, but each is taking its input frequency directly from the single pll. the pll has a frequency range of 2.44ghz to 2.6ghz. the divide ratios, settings and possible output frequencies are shown in table 3 . fractional output divider programming (q3 only) for the fracn output divider q[3], the output divide ratio is given by: ? output divide ratio = (n.f)x2 ? n = integer part: 4, 5, ...(2 18 -1) ? f = fractional part: [0, 1, 2, ...(2 28 -1)]/(2 28 ) for integer operation of this output dividers, n = 3 is also supported for the full output frequency range. output divider frequency sources output dividers associated with the q[0:2] outputs take their input frequency directly from the pll. the output divider associated with the q[3] output can take its input frequency from the pll, the clk0 or clk1 input reference frequency or the crystal frequency. output phase control on switchover there are two options on how the output phase can be controlled when the 8t49n240 enters or leaves the holdover state, or the p ll switches between input references. phase-slope limiting or fully hitless switching (sometimes called phase build-out) may be se lected. the swmode bit selects which behavior is to be followed. if fully hitless switching is selected, then the output phase will remain unchanged under any of these conditions. note that fu lly hitless switching is not supported when external loop-back is being used. if phase-slope limiting is selected, then the output phase will adjust from its previous value until it is tracking the new con dition at a rate dictated by the slew[1:0] bits. table 3. output divide ratios divide ratio minimum f out (mhz) maximum f out (mhz) 3 813.33 866.67 4 610 650 5 488 520 6 406.67 433.33 8 305 325 10 244 260 ... 160 15.25 16.25
10 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet output drivers the q0 to q3 clock outputs are provided with register-controlled output drivers. by selecting the output drive type in the appr opriate register, any of these outputs can support lvpecl, hcsl or lvds logic levels. in addition, the q3 output can support lvcmos operation. please refer to the section below for behavior if this option is selec ted for q3. the operating voltage ranges of each output is determined by its independent output power pin (v cco ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential operation and lvcmos operation. in addition, lvcmos output operation supports 1.8v v cco . each output may be enabled or disabled by register bits and/or gpio pins. lvcmos operation (q3 only) when the q3 output is configured to provide lvcmos levels, then both the q and nq outputs will toggle at the selected output fr equency. all the previously described configuration and control apply equally to both outputs. frequency, voltage levels and enable / di sable status apply to both the q and nq pins. when configured as lvcmos, the q and nq outputs can be selected to be phase-aligned with each other or inverted relative to one another. selection of phase-alignment may have negative effects on the phase noise performanc e of any part of the device due to increased simultaneous switching noise within the device. power-saving modes to allow the device to consume the least power possible for a given application, the following functions are included under reg ister control: ? any unused output, including all output divider logic, can be individually powered-off. ? any unused input, including the clock monitoring logic can be individually powered-off. ? the digital pll can be powered-off when running in synthesizer mode. ? clock gating on logic that is not being used. status / control signals and interrupts the status and control signals for the device, may be operated at 1.8v, 2.5v or 3.3v as determined by the voltage applied to th e v cccs pin. all signals will share the same voltage levels. signals involved include: nint, nrst, gpio[3:0], s_a0, s_a1, sclk and sdata. the voltage used here is independent of the voltag e chosen for the digital and analog core voltages and the output voltages selected for the clock outputs. general-purpose i/os and interrupts the 8t49n240 provides four general purpose input / output (gpio) pins for miscellaneous status and control functions. each gpio may be configured as either an input or an output. each gpio may be directly controlled from register bits or be used as a predefin ed function as shown in table 4 . note that the default state prior to configuration being loaded from internal otp will be to set each gpio to input direction to function as an output enable. table 4. gpio configuration gpio pin configured as input configured as output fixed function (default) general purpose fixed function general purpose 3 - gpi[3] lol gpo[3] 2 csel gpi[2] los[0] gpo[2] 1 osel[1] gpi[1] los[1] gpo[1] 0 osel[0] gpi[0] hold gpo[0]
11 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet if used in the fixed function mode of operation, the gpio bits will reflect the real-time status of their respective status bit s as shown in table 4 . the lol alarm will support two modes of operation: ? de-asserts once pll is locked, or ? de-asserts after pll is locked and all internal synchronization operations that may destabilize output clocks are completed. interrupt functionality interrupt functionality includes an interrupt status flag for each of pll loss-of-lock status (lol), pll in holdover status (ho ld) and loss-of-signal status for each input (los[1:0]). those status flags are set whenever there is an alarm on their respective func tions. the status flag will remain set until the alarm has been cleared and a ?1? has been written to the status flag?s register location or if a reset occurs. each status flag will also have an interrupt enable bit that will determine if that status flag is allowed to cause the device interrupt status to be affected (enabled) or not (disabled). all interrupt enable bits will be in the disabled state after rese t. the device interrupt status flag and nint output pin are asserted if any of the enabled interrupt status flags are set. output enable operation when gpio[1:0] are used as output enable control signals, the function of the pins is to select one of four register-based maps that indicate which outputs should be enabled or disabled. figure 3. output enable map operation in order to enable a clock output x (x = 0, 1, 2, or 3), three conditions must be met: ? the output must be powered (qx_dis = 0). ? the output must be enabled via registers (outen[x] = 1). ? if the gpio[1:0] are configured as osel[1:0] respectively, the output enable select pins (osel[1:0]) must select an output enab le map that enables output x (see figure 3 ). en en en en 0 0 q0 dis en en dis 0 1 en dis en dis 1 0 dis dis dis dis 1 1 q1 q2 q3 4 osel[1] osel[0]
12 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet device hardware configuration the 8t49n240 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with one complete device configuration. some or all of this pre-programmed configuration will be loaded into the device?s registers on p ower-up or reset. these default register settings can be over-written using the serial programming interface once reset is complete. any configur ation written via the serial programming interface needs to be re-written after any power cycle or reset. please contact idt if a spe cific factory-programmed configuration is desired. device start-up and reset behavior the 8t49n240 has an internal power-up reset (por) circuit and a master reset input pin nrst. if either is asserted, the device will be in the reset state. while in the reset state (nrst input asserted or por active), the device will operate as follows: ? all registers will return to and be held in their default states as indicated in the applicable register description. ? all internal state machines will be in their reset conditions. ? the serial interface will not respond to read or write cycles. ? the gpio signals will be configured as output enable inputs. ? all clock outputs will be disabled. ? all interrupt status and interrupt enable bits will be cleared, negating the nint signal. upon the later of the internal por circuit expiring or the nrst input negating, the device will exit reset and begin self-confi guration. the device will load an initial block of its internal registers using the configuration stored in the internal one-time program mable (otp) memory. once this step is complete, the 8t49n240 will check the register settings to see if it should load the remainder of its configuration from an external i 2 c eeprom at a defined address or continue loading from otp, or both. see the section on i 2 c boot initialization for details on how this is performed. once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock th e pll to the crystal and begin operation. once the pll is locked, all the outputs derived from it will be synchronized.
13 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration, to allow access to any of the internal registers for device programming or examination of internal status. all registers are configured to have default value s. see the specifics for each register for details. the device has the additional capability of becoming a master on the i 2 c bus only for the purpose of reading its initial register configurations from a serial eeprom on the i 2 c bus. writing of the configuration to the serial eeprom must be performed by another device on the same i 2 c bus or pre-programmed into the device prior to assembly. i 2 c mode operation the i 2 c interface is designed to fully support v1.2 of the i 2 c specification for normal and fast mode operation. the device acts as a slave device on the i 2 c bus at 100khz or 400khz using the address defined in the serial interface control register (0006h), as modified by the s_a0and s_a1 input pin settings. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed i n sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at which point, a ll data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 51k ? typical. figure 4. i 2 c slave read and write cycle sequencing current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data ? n a p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n a p offset ? addr ? msb a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master offset ? addr ? lsb a offset ? addr ? msb a offset ? addr ? lsb a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge a= ? none ? acknowledge p ? = ? stop
14 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet i 2 c master mode when operating in i 2 c mode, the 8t49n240 has the capability to become a bus master on the i 2 c bus for the purposes of reading its configuration from an external i 2 c eeprom. only a block read cycle will be supported. as an i 2 c bus master, the 8t49n240 will support the following functions: ? 7-bit addressing mode ? base address register for eeprom ? validation of the read block via ccitt-8 crc check against value stored in last byte (84h) of eeprom ? support for 100khz and 400khz operation with speed negotiation. if bit d0 is set at byte address 05h in the eeprom, this will s hift from 100khz operation to 400khz operation. ? support for 1- or 2-byte addressing mode ? master arbitration with programmable number of retries ? fixed-period cycle response timer to prevent permanently hanging the i 2 c bus. ? read will abort with an alarm (bootfail) if any of the following conditions occur: slave nack, arbitration fail, collision duri ng address phase, crc failure, slave response time-out the 8t49n240 will not support the following functions: ? i 2 c general call ? slave clock stretching ? i 2 c start byte protocol ? eeprom chaining ? cbus compatibility ? responding to its own slave address when acting as a master ? writing to external i 2 c devices including the external eeprom used for booting figure 5. i 2 c master read cycle sequencing sequential ? read ? (1 \ byte ? offset ? address) s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n a p sr dev ? addr ? + ? r a offset ? addr a sequential ? read ? (2 \ byte ? offset ? address) s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n a p offset ? addr ? msb a sr dev ? addr ? + ? r a offset ? addr ? lsb a from ? master ? to ? slave from ? slave ? to ? master s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge a= ? none ? acknowledge p ? = ? stop
15 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet i 2 c boot-up initialization mode if enabled (via the boot_eep bit in the startup register), once the nrst input has been deasserted (high) and its internal powe r-up reset sequence has completed, the device will contend for ownership of the i 2 c bus to read its initial register settings from a memory location on the i 2 c bus. the address of that memory location is kept in non-volatile memory in the startup register. during the boot-up process, the device will not respond to serial control port accesses. once the initialization process is complete, the contents of any of the device?s registers can be altered. it is the responsibility of the user to make any desired adjustments in initial values direc tly in the serial bus memory. if a nack is received to any of the read cycles performed by the device during the initialization process, or if the crc does n ot match the one stored in address 84h of the eeprom the process will be aborted and any uninitialized registers will remain with their defa ult values. the bootfail bit in the global interrupt status register (0210h) will also be set in this event. contents of the eeprom should be as shown in table 5 . table 5. external serial eeprom contents eeprom offset (hex) contents d7 d6 d5 d4 d3 d2 d1 d0 00 1111111 1 01 1111111 1 02 1111111 1 03 1111111 1 04 1111111 1 05 1111111 serial eeprom speed select 0 = 100khz 1 = 400khz 06 1 8t49n240 device i 2 c address [6:2] 1 1 07 0000000 0 08 - 83 desired contents of device registers 08h - 83h 84 serial eeprom crc 85 - ff unused
16 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet register descriptions table 6. register blocks register ranges offset (hex) register block description 0000?0001 startup control registers 0002?0005 device id control registers 0006?0007 serial interface control registers 0008?002f digital pll control registers 0030?0038 gpio control registers 0039?003e output driver control registers 003f?004a output divider control registers (integer portion) 004b?0056 reserved 0057?0062 output divider control registers (fractional portion) 0063?0067 output divider source control registers 0068?006c analog pll control registers 006d?0070 power-down and lock alarm control registers 0071?0078 input monitor control registers 0079 interrupt enable register 007a?007b reserved 007c?01ff reserved 0200?0201 interrupt status registers 0202?020b reserved 020c general-purpose input status register 020d?0211 global interrupt and boot status register 0212?03ff reserved
17 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 7. startup control register bit field locations and descriptions startup control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0000 eep_rty[4:0] rsvd nboot_otp nboot_eep 0001 eep_a15 eep_addr[6:0] startup control register block field descriptions bit field name field type default value description eep_rty[4:0] r/w 1h select number of times arbitration for the i 2 c bus to read the serial eeprom will be retried before being aborted. note that this number does not include the original try. nboot_otp r/w note [a] internal one-time programmable (otp) memory usage on power-up: 0 = load power-up configuration from otp 1 = only load 1st eight bytes from otp nboot_eep r/w note a external eeprom usage on power-up: 0 = load power-up configuration from external serial eeprom (overwrites otp values) 1 = don?t use external eeprom eep_a15 r/w note a serial eeprom supports 15-bit addressing mode (multiple pages). eep_addr[6:0] r/w note a i 2 c base address for serial eeprom. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. [a] these values are specific to the device configuration and can be customized when ordering. please refer to the femtoclock ? ng universal frequency translator ordering product information guide for exact default values.
18 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 8. device id control register bit field locations and descriptions device id register control block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0002 rev_id[3:0] dev_id[15:12] 0003 dev_id[11:4] 0004 dev_id[3:0] dash_code [10:7] 0005 dash_code [6:0] 1 device id control register block field descriptions bit field name field type default value description rev_id[3:0] r/w 0h device revision. dev_id[15:0] r/w 060ch device id code. dash code [10:0] r/w note [a] device dash code. decimal value assigned by idt to identify the configuration loaded at the factory. may be over-written by users at any time. [a] these values are specific to the device configuration and can be customized when ordering. please refer to the femtoclock ? ng universal frequency translator ordering product information guide for exact default values. table 9. serial interface control register bit field locations and descriptions serial interface control block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0006 rsvd uftadd[6:2] uftadd[1] uftadd[0] 0007 rsvd rsvd serial interface control register block field descriptions bit field name field type default value description uftadd[6:2] r/w note [a] [a] these values are specific to the device configuration ?dash-code?. please refer to the femtoclock ng universal frequency translator ordering product information guide for exact default values. configurable portion of i 2 c base address for this device. uftadd[1] r/o 0b i 2 c base address bit 1. see table 1. this address bit reflects the status of the s_a1 external input pin. uftadd[0] r/o 0b i 2 c base address bit 0. this address bit reflects the status of the s_a0 external input pin. see table 1. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
19 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 10. digital pll input control regi ster bit field locations and descriptions digital pll input control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0008 refsel[2:0] fbsel[2:0] rvrt swmode 0009 rsvd ref_pri 000a rsvd refdis1 refdi s0 rsvd rsvd state[1:0] 000b rsvd pre0[20:16] 000c pre0[15:8] 000d pre0[7:0] 000e rsvd pre1[20:16] 000f pre1[15:8] 0010 pre1[7:0] digital pll input control register block field descriptions bit field name field type default value description refsel[2:0] r/w 000b input reference selection for digital pll: 000 = automatic selection 001 = manual selection by gpio input 010 through 011 = reserved 100 = force selection of input reference 0 101 = force selection of input reference 1 110 = do not use 111 = do not use fbsel[2:0] r/w 000b feedback mode selection for digital pll: 000 through 011 = internal feedback divider 100 = external feedback from input reference 0 101 = external feedback from input reference 1 110 = do not use 111 = do not use rvrt r/w 1b automatic switching mode for digital pll: 0 = non-revertive switching 1 = revertive switching swmode r/w 1b controls how digital pll adjusts output phase when switching between input references: 0 = absorb any phase differences between old and new input references 1 = track to follow new input reference?s phase using phase-slope limiting ref_pri r/w 0b switchover priority for input references when used by digital pll: 0 = clk0 is primary input reference 1 = clk1 is primary input reference
20 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet refdis1 r/w 0b input reference 1 switching selection disable for digital pll: 0 = input reference 1 is included in the switchover sequence 1 = input reference 1 is not included in the switchover sequence refdis0 r/w 0b input reference 0 switching selection disable for digital pll: 0 = input reference 0 is included in the switchover sequence 1 = input reference 0 is not included in the switchover sequence state[1:0] r/w 00b digital pll state machine control: 00 = run automatically 01 = force freerun state - set this if in synthesizer mode. 10 = force normal state 11 = force holdover state pre0[20:0] r/w 000000h pre-divider ratio for input reference 0 when used by digital pll. pre1[20:0] r/w 000000h pre-divider ratio for input reference 1 when used by digital pll. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. digital pll input control register block field descriptions bit field name field type default value description
21 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 11. digital pll feedback control re gister bit field locations and descriptions digital pll feedback control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0011 m1_0[23:16] 0012 m1_0[15:8] 0013 m1_0[7:0] 0014 m1_1[23:16] 0015 m1_1[15:8] 0016 m1_1[7:0] 0017 lckbw[3:0] acqbw[3:0] 0018 lckdamp[2:0] acqdamp[2:0] pllgain[1:0] 0019 rsvd rsvd rsvd rsvd 001a rsvd 001b rsvd 001c rsvd rsvd 001d rsvd 001e rsvd 001f ffh 0020 ffh 0021 ffh 0022 ffh 0023 slew[1:0] rsvd hold[1:0] rsvd holdavg fastlck 0024 lock[7:0] 0025 rsvd dsm_int[8] 0026 dsm_int[7:0] 0027 rsvd 0028 rsvd dsmfrac[20:16] 0029 dsmfrac[15:8] 002a dsmfrac[7:0] 002b 00h 002c 01h 002d rsvd 002e rsvd 002f dsm_ord[1:0] dcxogain[1:0] rsvd dithgain[2:0]
22 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet digital pll feedback configuration register block field descriptions bit field name field type default value description m1_0[23:0] r/w 070000h m1 feedback divider ratio for input reference 0 when used by digital pll. m1_1[23:0] r/w 070000h m1 feedback divider ratio for input reference 1 when used by digital pll. lckbw[3:0] r/w 0111b digital pll loop bandwidth while locked: 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved acqbw[3:0] r/w 0111b digital pll loop bandwidth while in acquisition (not-locked): 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved
23 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet lckdamp[2:0] r/w 011b damping factor for digital pll while locked: 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved acqdamp[2:0] r/w 011b damping factor for digital pll while in acquisition (not locked): 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved pllgain[1:0] r/w 01b digital loop filter gain settings for digital pll: 00 = 0.5 01 = 1 10 = 1.5 11 = 2 slew[1:0] r/w 00b phase-slope control for digital pll: 00 = no limit - controlled by loop bandwidth of digital pll 01 = 64us/s 10 = 11us/s 11 = reserved hold[1:0] r/w 00b holdover averaging mode selection for digital pll: 00 = instantaneous mode - uses historical value 100ms prior to entering holdover 01 = fast average mode 10 = reserved 11 = return to center of vco tuning range holdavg r/w 0b holdover averaging enable for digital pll: 0 = holdover averaging disabled 1 = holdover averaging enabled as defined in hold[1:0] fastlck r/w 0b enables fast lock operation for digital pll: 0 = normal locking using lckbw and lckdamp fields in all cases 1 = fast lock mode using acqbw and acqdamp when not phase locked and lckbw and lckdamp once phase locked digital pll feedback configuration register block field descriptions bit field name field type default value description
24 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet lock[7:0] r/w 3fh lock window size for digital pll. unsigned 2?s complement binary number in steps of 2.5ns, giving a total range of 640ns. do not program to 0. dsm_int[8:0] r/w 02dh integer portion of the delta-sigma modulator value. dsmfrac[20:0] r/w 000000h fractional portion of delta-sigma modulator value. divide this number by 2 21 to determine the actual fraction. dsm_ord[1:0] r/w 11b delta-sigma modulator order for digital pll: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation dcxogain[1:0] r/w 01b multiplier applied to instantaneous frequency error before it is applied to the digitally controlled oscillator in digital pll: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain[2:0] r/w 000b dither gain setting for digital pll: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. digital pll feedback configuration register block field descriptions bit field name field type default value description
25 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 12. gpio control register bit field locations and descriptions the values observed on any gpio pins that are used as general purpose inputs are visible in the gpi[3:0] register that is locat ed at location 0x020c near a number of other read-only registers. gpio control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0030 rsvd gpio_dir[3:0] 0031 rsvd gpi3sel[2] gpi2sel[2] gpi1sel[2] gpi0sel[2] 0032 rsvd gpi3sel[1] gpi2sel[1] gpi1sel[1] gpi0sel[1] 0033 rsvd gpi3sel[0] gpi2sel[0] gpi1sel[0] gpi0sel[0] 0034 rsvd gpo3sel[2] gpo2sel[2] gpo1sel[2] gpo0sel[2] 0035 rsvd gpo3sel[1] gpo2sel[1] gpo1sel[1] gpo0sel[1] 0036 rsvd gpo3sel[0] gpo2sel[0] gpo1sel[0] gpo0sel[0] 0037 rsvd 0038 rsvd gpo[3:0] gpio control register block field descriptions bit field name field type default value description gpio_dir[3:0] r/w 0000b direction control for general-purpose i/o pins gpio[3:0]: 0 = input mode 1 = output mode gpi3sel[2:0] r/w 001b function of gpio[3] pin when set to input mode by gpio_dir[3] register bit: 000 = general purpose input (value on gpio[3] pin directly reflected in gpi[3] register bit) 001 = reserved 010 = reserved 011 = reserved 100 through 111 = reserved gpi2sel[2:0] r/w 001b function of gpio[2] pin when set to input mode by gpio_dir[2] register bit: 000 = general purpose input (value on gpio[2] pin directly reflected in gpi[2] register bit) 001 = csel: manual clock select input for pll 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved
26 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet gpi1sel[2:0] r/w 001b function of gpio[1] pin when set to input mode by gpio_dir[1] register bit: 000 = general purpose input (value on gpio[1] pin directly reflected in gpi[1] register bit) 001 = output enable control bit 1: osel[1] 010 through 111 = reserved gpi0sel[2:0] r/w 001b function of gpio[0] pin when set to input mode by gpio_dir[0] register bit: 000 = general purpose input (value on gpio[0] pin directly reflected in gpi[0] register bit) 001 = output enable control bit 0: osel[0] 010 = reserved 011 = reserved 100 through 111 = reserved gpo3sel[2:0] r/w 000b function of gpio[3] pin when set to output mode by gpio_dir[3] register bit: 000 = general purpose output (value in gpo[3] register bit driven on gpio[3] pin 001 = loss-of-lock status flag for digital pll reflected on gpio[3] pin 010 = reserved 011 = reserved 100 through 111 = reserved gpo2sel[2:0] r/w 000b function of gpio[2] pin when set to output mode by gpio_dir[2] register bit: 000 = general purpose output (value in gpo[2] register bit driven on gpio[2] pin 001 = loss-of-signal status flag for input reference 0 reflected on gpio[2] pin 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved gpo1sel[2:0] r/w 000b function of gpio[1] pin when set to output mode by gpio_dir[1] register bit: 000 = general purpose output (value in gpo[1] register bit driven on gpio[1] pin 001 = loss-of-signal status flag for input reference 1 reflected on gpio[1] pin 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved gpio control register block field descriptions bit field name field type default value description
27 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet gpo0sel[2:0] r/w 000b function of gpio[0] pin when set to output mode by gpio_dir[0] register bit: 000 = general purpose output (value in gpo[0] register bit driven on gpio[0] pin 001 = holdover status flag for digital pll reflected on gpio[0] pin 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 through 111 = reserved gpo[3:0] r/w 00h output values reflect on pin gpio[3:0] when general-purpose output mode selected. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. gpio control register block field descriptions bit field name field type default value description
28 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 13. output driver control register bit field locations and descriptions output driver control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0039 rsvd outen[3:0] 003a rsvd pol_q[3] rsvd 003b rsvd 003c rsvd 003d outmode3[2:0] se_mode3 outmode2[2:0] rsvd 003e outmode1[2:0] rsvd outmode0[2:0] rsvd output driver control register block field descriptions bit field name field type default value description outen[3:0] r/w 0000b output enable control for clock outputs q[3:0], nq[3:0]: 0 = qn is in a high-impedance state 1 = qn is enabled as indicated in appropriate outmoden[2:0] register field pol_q[3] r/w 0000b polarity of clock outputs q[3], nq[3]: 0 = q3 is normal polarity 1 = q3 is inverted polarity outmode3[2:0] r/w 001b output driver mode of operation for clock output pair q3, nq3: 000 = high-impedance 001 = lvpecl 010 = lvds 011 = lvcmos 100 = hcsl 101 - 111 = reserved se_mode3 r/w 0b behavior of output pair q3, nq3 when lvcmos operation is selected: (must be 0 if lvds or lvpecl output style is selected) 0 = q3 and nq3 are both the same frequency but inverted in phase 1 = q3 and nq3 are both the same frequency and phase outmodem[2:0] r/w 001b output driver mode of operation for clock output pair qm, nqm (m = 0, 1, 2): 000 = high-impedance 001 = lvpecl 010 = lvds 011 = reserved 100 = hcsl 101 - 111 = reserved rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
29 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 14. output divider control register (integer portion) bit field locations and descriptions output divider control register (integer portion) block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 003f n_q0[7:0] 0040 rsvd 0041 rsvd 0042 n_q1[7:0] 0043 rsvd 0044 rsvd 0045 n_q2[7:0] 0046 rsvd 0047 rsvd 0048 rsvd n_q3[17:16] 0049 n_q3[15:8] 004a n_q3[7:0] output divider control register (integer portion) block field descriptions bit field name field type default value description n_qm[7:0] r/w 03h 1st stage output divider ratio for output clock qm, nqm (m = 0, 1, 2): 00h - 02h = do not use 03h - 06h = actual divide ratio (e.g. 03h = /3, a0h = /160) 07h - a0h = even numbers represent actual divide ratio, odd numbers should not be used (07h = do not use, 08h = /8, 09h = do not use, 0ah = /10, etc.) a1h - ffh = do not use n_q3[17:0] r/w 20002h integer portion of output divider ratio for output clock q3, nq3: values of 0, 1 or 2 cannot be written to this register. actual divider ratio is 2x the value written here. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
30 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 15. output divider control register (fractional portion) bit field locations and descriptions (q3 only) output divider control register (fractional portion) block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0057 rsvd 0058 rsvd 0059 rsvd 005a rsvd 005b rsvd 005c rsvd 005d rsvd 005e rsvd 005f rsvd nfrac_q3[27:24] 0060 nfrac_q3[23:16] 0061 nfrac_q3[15:8] 0062 nfrac_q3[7:0] output divider control register (fractional portion) block field descriptions bit field name field type default value description nfrac_qm[27:0] r/w 0000000h fractional portion of output divider ratio for output clock q3, nq3. actual fractional portion is 2x the value written here. fraction = (nfrac_qm * 2) * 2 -28 rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
31 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 16. output clock source control register bit field locations and descriptions output clock source control re gister block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0063 pll_syn rsvd clk_sel3[1:0] rsvd 0064 rsvd 0065 rsvd 0066 rsvd rsvd rsvd rsvd 0067 10b 10b 00b rsvd output clock source control re gister block field descriptions bit field name field type default value description pll_syn r/w 0b output synchronization control for outputs derived from pll. setting this bit from 0->1 will cause the output divider(s) for the affected outputs to be held in reset. setting this bit from 1->0 will release all the output divider(s) for the affected outputs to run from the same point in time. clk_sel3[1:0] r/w 00b clock source selection for output pair q3: nq3. do not select input reference 0 or 1 if that input is faster than 250mhz: 00 = pll 01 = input reference 0 (clk0) 10 = input reference 1 (clk1) 11 = crystal input rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
32 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 17. analog pll control register bit field locations and descriptions please contact idt through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. analog pll control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0068 rsvd rs[2:0] wpst[1:0] wpst_by p 0069 rsvd rsvd tdc_dis syn_mode 1 dlcnt dbitm 006a vcoman[2:0] dbit[4:0] 006b 001b rsvd 006c rsvd cpset[4:0] analog pll control register block field descriptions bit field name field type default value description rs[2:0] r/w 001b internal loop filter series resistor setting for analog pll: 000 = 98 ? 001 = 107 ? 010 = 131 ? 011 = 168 ? 100 = 235 ? 101 = 294 ? 110 = 588 ? 111 = 1.18k ? wpst[1:0] r/w 01b internal loop filter 2nd-pole setting for analog pll: 00 = rpost = 510 ? , cpost = 120pf 01 = rpost = 510 ? , cpost = 160pf 10 = rpost = 510 ? , cpost = 200pf 11 = rpost = 510 ? , cpost = 240pf wpst_byp r/w 1b internal loop filter 2nd-pole bypass for analog pll: 0 = loop filter 2nd-pole is used 1 = loop filter 2nd-pole is not used tdc_dis r/w 0b tdc disable control for pll: 0 = tdc enabled 1 = tdc disabled syn_mode r/w 0b frequency synthesizer mode control for pll: 0 = pll jitter attenuates and translates one or more input references 1 = pll synthesizes output frequencies using only the crystal as a reference note that the state[1:0] field in the digital pll control register must be set to force freerun state.
33 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet dlcnt r/w 1b digital lock count setting for analog pll: 0 = counter is a 16-bit accumulator 1 = counter is a 20-bit accumulator dbitm r/w 0b digital lock manual override setting for analog pll: 0 = automatic mode 1 = manual mode vcoman[2:0] r/w 001b manual lock mode vco selection setting for analog pll: 000 = vco0 001 = vco1 010 - 111 = reserved dbit[4:0] r/w 01011b manual mode digital lock control setting for vco in analog pll. cpset[4:0] r/w 00000b charge pump current setting for analog pll: rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. analog pll control register block field descriptions bit field name field type default value description 00000 = 110 a 00001 = 220 a 00010 = 330 a 00011 = 440 a 00100 = 550 a 00101 = 660 a 00110 = 770 a 00111 = 880 a 01000 = 990 a 01001 = 1100 a 01010 = 1210 a 01011 = 1320 a 01100 = 1430 a 01101 = 1540 a 01110 = 1650 a 01111 = 1760 a 10000 = 165 a 10001 = 330 a 10010 = 495 a 10011 = 660 a 10100 = 825 a 10101 = 990 a 10110 = 1155 a 10111 = 1320 a 11000 = 1485 a 11001 = 1650 a 11010 = 1815 a 11011 = 1980 a 11100 = 2145 a 11101 = 2310 a 11110 = 2475 a 11111 = 2640 a
34 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 18. power down control register bit field locations and descriptions power down control regist er block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 006d rsvd clk1_dis clk0_dis 006e rsvd lckmode dbl_dis 006f rsvd q3_dis q2_dis q1_dis q0_dis 0070 rsvd dpll_dis dsm_dis calrst power down control register block field descriptions bit field name field type default value description clkm_dis r/w 0b disable control for input reference m: 0 = input reference m is enabled 1 = input reference m is disabled lckmode r/w 0b controls the behavior of the lol alarm deassertion: 0 = lol alarm deasserts once pll is locked 1 = lol alarm deasserts once pll is locked and output clocks are stable dbl_dis r/w 0b controls whether crystal input frequency is doubled before being used in pll: 0 = 2x actual crystal frequency used 1 = actual crystal frequency used qm_dis r/w 0b disable control for output qm, nqm: 0 = output qm, nqm functions normally 1 = all logic associated with output qm, nqm is disabled and driver in high-impedance state dpll_dis r/w 0b disable co ntrol for digital pll: 0 = digital pll enabled 1 = digital pll disabled dsm_dis r/w 0b disable control for delta-sigma modulator for analog pll: 0 = dsm enabled 1 = dsm disabled calrst r/w 0b reset calibration logic for apll: 0 = calibration logic for apllm enabled 1 = calibration logic for apllm disabled rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
35 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 19. input monitor control register bit field locations and descriptions input monitor control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0071 rsvd los_0[16] 0072 los_0[15:8] 0073 los_0[7:0] 0074 rsvd los_1[16] 0075 los_1[15:8] 0076 los_1[7:0] 0077 rsvd 0078 rsvd input monitor control register block field descriptions bit field name field type default value description los_m[16:0] r/w 1ffffh number of input monitoring clock periods before input reference m is considered to be missed (soft alarm). minimum setting is 3. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. table 20. interrupt enable control register bit field locations and descriptions interrupt enable control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0079 rsvd lol_en rsvd hold_en rsvd los1_en los0_en interrupt enable control register block field descriptions bit field name field type default value description lol_en r/w 0b interrupt enable control for loss-of-lock interrupt status bit: 0 = lol_int register bit will not affect status of nint output signal 1 = lol_int register bit will affect status of nint output signal hold_en r/w 0b interrupt enable control for holdover interrupt status bit: 0 = hold_int register bit will not affect status of nint output signal 1 = hold_int register bit will affect status of nint output signal losm_en r/w 0b interrupt enable control for loss-of-signal interrupt status bit for input reference m: 0 = losm_int register bit will not affect status of nint output signal 1 = losm_int register bit will affect status of nint output signal rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
36 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 21. interrupt status register bit field locations and descriptions this register contains ?sticky? bits for tracking the status of the various alarms. whenever an alarm occurs, the appropriate i nterrupt status bit will be set. the interrupt status bit will remain asserted even after the original alarm goes away. the interrupt st atus bits remain asserted until explicitly cleared by a write of a ?1? to the bit over the serial port. this type of functionality is ref erred to as read / write-1-to-clear (r/w1c). interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0200 rsvd lol_int rsvd hold_int rsvd los1_int los0_int 0201 rsvd interrupt status register block field descriptions bit field name field type default value description lol_int r/w1c 0b interrupt status bit for loss-of-lock: 0 = no loss-of-lock alarm flag on pll has occurred since the last time this register bit was cleared 1 = at least one loss-of-lock alarm flag on pll has occurred since the last time this register bit was cleared hold_int r/w1c 0b interrupt status bit for holdover: 0 = no holdover alarm flag has occurred since the last time this register bit was cleared 1 = at least one holdover alarm flag has occurred since the last time this register bit was cleared losm_int r/w1c 0b interrupt status bit for loss-of-signal on input reference m: 0 = no loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared 1 = at least one loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
37 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 22. digital pll status register bit field locations and descriptions digital pll status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0202 rsvd rsvd rsvd rsvd 0203 rsvd rsvd rsvd rsvd rsvd 0204 rsvd rsvd 0205 rsvd 0206 rsvd 0207 rsvd rsvd 0208 rsvd 0209 rsvd 020a rsvd rsvd 020b rsvd digital pll status register block field descriptions bit field name field type default value description rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. table 23. general purpose input status register bit field locations and descriptions global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020c rsvd gpi[3] gpi[2] gpi[1] gpi[0] general purpose input status register block field descriptions bit field name field type default value description gpi[3:0] r/o - shows current values on gpio[3:0] pins that are configured as general-purpose inputs. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
38 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 24. global interrupt status register bit field locations and descriptions global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020d rsvd rsvd rsvd int 020e rsvd rsvd 020f rsvd rsvd 0210 rsvd rsvd eep_err bootfail 0211 rsvd rsvd rsvd rsvd rsvd rsvd rsvd eepdone 0212 rsvd global interrupt status register block field descriptions bit field name field type default value description int r/o - device interrupt status: 0 = no interrupt status bits that are enabled are asserted (nint pin released) 1 = at least one interrupt status bit that is enabled is asserted (nint pin asserted low) eep_err r/o - crc mismatch on eeprom read. once set this bit is on ly cleared by reset. bootfail r/o - reading of serial eeprom failed. once set this bit is only cleared by reset. eepdone r/o - serial eeprom read cycle has completed. once set this bit is only cleared by reset. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
39 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. table 25. absolute maximum ratings table item rating supply voltage, v cc 3.63v inputs, v i osci [a] other input [a] this limit only applies when over-driving the osci input from an external clock source. when used with a crystal, this limit does not apply. 0v to 2v -0.5v to v cc + 0.5v outputs, v o (q[3:0], nq[3:0]) -0.5v to v ccox [b] + 0.5v [b] v ccox denotes: v cco0 , v cco1 , v cco2 , v cco3 . outputs, v o (gpio[3:0], sclk, sdata, nint) -0.5v to v cccs + 0.5v outputs, i o (q[3:0], nq[3:0]) continuous current surge current 40ma 65ma outputs, i o (gpio[3:0], sclk, sdata, nint)) continuous current surge current 8ma 13ma junction temperature, t j 125 ? c storage temperature, t stg -65 ? c to 150 ? c
40 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet supply voltage characteristics table 26. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 v cc v v cccs control and status supply voltage [a] [a] gpio [3:0], sdata, sclk, s_a1, s_ a0, nint, nrst pins are floating. 1.71 v cc v i cc core supply current [b] [b] i cc , i cccs, and i cca are included in i ee when q[0:3] configured for lvpecl logic levels. 40 53 ma i cccs control and status supply current [b] 35ma i cca analog supply current [b] 140 186 ma i ee power supply current [c] [c] internal dynamic switching current at maximum f out is included. q[0:3] configured for lvpecl logic levels. outputs unloaded 345 438 ma
41 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 27. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage 2.375 2.5 v cc v v cccs control and status supply voltage [a] 1.71 v cc v i cc core supply current [b] 39 50 ma i cccs control and status supply current [b] 35ma i cca analog supply current [b] 135 179 ma i ee power supply current [c] q[0:3] configured for lvpecl logic levels. outputs unloaded 328 415 ma [a] gpio [3:0], sdata, sclk, s_a1, s_ a0, nint, nrst pins are floating. [b] i cc , i cccs, and i cca are included in i ee when q[0:3] configured for lvpecl logic levels. [c] internal dynamic switching current at maximum f out is included. table 28. maximum output supply current, v cc = v cccs = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox [a] = 3.3v 5% [a] v ccox denotes v cco0 , v cco1 , v cco2 , v cco3 . v ccox [a] = 2.5v 5% v ccox [a] = 1.8v 5% units lvpecl lvds hcsl lvcmos lvpecl lvds hcsl lvcmos lvcmos i cco0 [b] [b] internal dynamic switching current at maximum f out is included. q0, nq0 output supply current outputs unloaded 50 60 50 n/a 44 52 44 n/a n/a ma i cco1 [b] q1, nq1 output supply current outputs unloaded 52 63 52 n/a 45 54 45 n/a n/a ma i cco2 [b] q2, nq2 output supply current outputs unloaded 52 61 52 n/a 45 54 45 n/a n/a ma i cco3 [b] q3, nq3 output supply current outputs unloaded 58 67 58 63 52 61 52 56 52 ma
42 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet dc electrical characteristics table 29. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c [a] [a] v il should not be less than -0.3v. symbol parameter test conditions minimum typical maximum units v ih input high voltage gpio[3:0], sdata, sclk, nrst, s_a0, s_a1 v cccs = 3.3v 2.1 v cccs +0.3 v v cccs = 2.5v 1.7 v cccs +0.3 v v cccs = 1.8v 1.4 v cccs +0.3 v v il input low voltage gpio[3:0], sdata, sclk, nrst, s_a0, s_a1 v cccs = 3.3v -0.3 0.8 v v cccs = 2.5v -0.3 0.6 v v cccs = 1.8v -0.3 0.4 v i ih input high current s_a0, s_a1 v cccs = v in = 3.465v, 2.625v, 1.89v 150 ? a nrst, sdata, sclk v cccs = v in = 3.465v, 2.625v, 1.89v 5 ? a gpio[3:0] v cccs = v in = 3.465v, 2.625v, 1.89v 1 ma i il input low current s_a0, s_a1 v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -5 ? a nrst, sdata, sclk v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -150 ? a gpio[3:0] v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -1 ma v oh output high voltage gpio[3:0] v cccs = 3.3v 5%, i oh = -2ma 2.4 v sdata, sclk, nint [b] [b] use of external pull-up resistors is recommended for the sdata, sclk, nint pins. v cccs = 1.8v 5%, i oh = -5a gpio[3:0] v cccs = 2.5v 5%, i oh = -1ma 1.7 v sdata, sclk, nint [b] v cccs = 2.5v 5%, i oh = -5 a gpio[3:0] v cccs = 1.8v 5%, i oh = -5 av cccs -0.45v v sdata, sclk, nint [b] v ol output low voltage sdata, sclk, nint, gpio[3:0] b v cccs = 3.3v 5%, i ol = 2ma 0.4 v v cccs = 2.5v5%, i ol = 1ma 0.4 v v cccs = 1.8v5%, i ol = 2ma 0.45 v table 30: differential input dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter [a] [a] clkx denotes clk0, clk1. nclkx denotes nclk0, nclk1 test conditions minimum typical maximum units i ih input high current clkx, nclkx v cc = v in = 3.465v or 2.625v 150 ? a i il input low current clkx v cc = 3.465v or 2.625v, v in = 0v -5 ? a nclkx v cc = 3.465v or 2.625v, v in = 0v -150 ? a v pp peak-to-peak voltage [b] [b] v il should not be less than -0.3v. v ih should not be higher than v cc . 0.15 1.3 v v cmr common mode input voltage b, [c] [c] common mode voltage is defined as the cross-point. v ee v cc -1.2 v
43 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 31. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox [a] = 3.3v5% v ccox a = 2.5v5% units minimum typical maximum minimum typical maximum v oh output high voltage [b] v ccox - 1.3 v ccox - 0.8 v ccox - 1.4 v ccox - 0.9 v v ol output low voltage b v ccox - 1.95 v ccox - 1.75 v ccox - 1.95 v ccox - 1.75 v [a] v ccox denotes v cco0 , v cco1 , v cco2 , v cco3 . [b] outputs terminated with 50 ? to v ccox ? 2v. table 32. lvds dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox [a] = 3.3v 5% or 2.5v 5%, v ee =0v, t a = -40c to 85c [b] [a] v ccox denotes v cco0 , v cco1 , v cco2 , and v cco3 . [b] terminated with 100 ? across qx and nqx. symbol parameter test conditions minimum typical maximum units v od differential output voltage [c],[d] [c] v od (differential output voltage) refers to a single-ended value (swing of negative or positive signal only), not a differential value. differential values can be obtained by doubling the single-ended measurement shown in this table. [d] v od specification also applies to output frequencies 125mhz. 250 450 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.375 v ? v os v os magnitude change 50 mv table 33. lvcmos dc characteristics (q3 only), v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v cco3 = 3.3v5% v cco3 = 2.5v5% v cco3 = 1.8v 5% units min. typ. max. min. typ. max. min. typ. max. v oh output high voltage i oh = -8ma 2.8 2.0 1.2 v v ol output low voltage i ol = 8ma 0.3 0.4 0.5 v
44 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 34. input frequency characteristics, v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f in input frequency [a] osci, osco using a crystal (see table 35 for crystal characteristics) 10 54 mhz over-driving crystal input doubler logic enabled [b] 10 54 mhz over-driving crystal input doubler logic disabled [b] 10 108 mhz clkx, nclkx [c] 0.008 875 mhz f pd phase detector frequency [d] 0.008 8 mhz f sclk serial port clock sclk (slave mode) i 2 c operation 100 400 khz [a] for the input reference frequency, the divider values must be set for the vco to operate within its supported range. [b] for optimal noise performance, the use of a quartz crystal is recommended (for more information, see overdriving the xtal interface ). [c] clkx denotes clk0, clk1; nclkx denotes nclk0, nclk1. [d] pre-dividers must be used to divide the clkx frequency down to an f pd valid frequency range. table 35. crystal characteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 10 54 mhz equivalent series resistance (esr) 15 30 ? load capacitance (c l ) crystal frequency ? 40mhz 12 pf crystal frequency ?? 40mhz 12 pf frequency stability (total) -100 100 ppm
45 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet ac electrical characteristics table 36. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (lvcmos logic levels only), t a = -40c to 85c [a], [b] symbol parameter test conditions min. typ. max. units f vco vco operating frequency 2440 2600 mhz f out output frequency lvpecl, lvds, hcsl q0, q1, q2 outputs 15.25 866.67 mhz q3 output integer divide 0.008 433.33 mhz q3 output non-integer divide 0.008 325 lvcmos 0.008 250 mhz t r / t f output rise and fa ll times lvpecl 20% to 80% 320 500 ps lvds 20% to 80%, v ccox = 3.3v 200 280 ps 20% to 80%, v ccox = 2.5v 200 400 ps hcsl 20% to 80% 270 470 ps lvcmos [c], [d] 20% to 80%, v ccox = 3.3v 200 310 ps 20% to 80%, v ccox = 2.5v 240 360 ps 20% to 80%, v ccox = 1.8v 350 550 ps sr output slew rate lvpecl differential waveform, measured 150mv from center 25.5v/ns lvds differential waveform, measured 150mv from center v ccox = 2.5v 14v/ns v ccox = 3.3v 1.5 5 v/ns hcsl measured on differential waveform, 150mv from center, v ccox = 2.5v 24.8v/ns measured on differential waveform, 150mv from center, v ccox = 3.3v 37v/ns t sk(b) bank skew [e], [f], [g], [h] lvpecl q[0:2], nq[0:2] 50 ps lvds q[0:2], nq[0:2] 50 ps hcsl q[0:2], nq[0:2] 50 ps odc output duty cycle [i] lvpecl, lvds, hcsl 45 50 55 % lvcmos 40 50 60 % ? spo static phase offset variation f in =f out =156.25 mhz [j] -250 250 ps initial frequency offset [k], [l], [m] switchover or entering / leaving holdover state -50 50 ppb output phase change in fully hitless switching [n] switchover or entering / leaving holdover state 2ns
46 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet ? ssb (1) single sideband phase noise [o] 1hz 122.88mhz output jitter attenuator mode input frequency: 25mhz, xtal frequency: 40.8mhz -51 dbc/hz ? ssb (10) 10hz -67 dbc/hz ? ssb (100) 100hz -69 dbc/hz ? ssb (1k) 1khz -107 dbc/hz ? ssb (10k) 10khz -128 dbc/hz ? ssb (100k) 100khz -136 dbc/hz ? ssb (1m) 1mhz -155 dbc/hz ? ssb (10m) 10mhz -161 dbc/hz ? ssb (30m) > 30mhz -162 dbc/hz ? ssb (1) single sideband phase noise [p] 1hz 156.25mhz output jitter attenuator mode input frequency: 25mhz xtal frequency: 49.152mhz -45 dbc/hz ? ssb (10) 10hz -64 dbc/hz ? ssb (100) 100hz -74 dbc/hz ? ssb (1k) 1khz -105 dbc/hz ? ssb (10k) 10khz -129 dbc/hz ? ssb (100k) 100khz -134 dbc/hz ? ssb (1m) 1mhz -152 dbc/hz ? ssb (10m) 10mhz -159 dbc/hz ? ssb (30m) > 30mhz -160 dbc/hz ? ssb (1) single sideband phase noise [q] 1hz 161.1328125mhz output fractional feedback synthesizer mode xtal frequency: 49.152mhz -25 dbc/hz ? ssb (10) 10hz -61 dbc/hz ? ssb (100) 100hz -95 dbc/hz ? ssb (1k) 1khz -122 dbc/hz ? ssb (10k) 10khz -127 dbc/hz ? ssb (100k) 100khz -135 dbc/hz ? ssb (1m) 1mhz -152 dbc/hz ? ssb (10m) 10mhz -155 dbc/hz ? ssb (30m) > 30mhz -159 dbc/hz spurious limit at offset [r] > 800khz 156.25mhz lvpecl output -85 dbc table 36. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (lvcmos logic levels only), t a = -40c to 85c [a], [b] (cont.) symbol parameter test conditions min. typ. max. units
47 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet t startup startup time internal otp startup l from v cc >80% to first output clock edge 120 150 ms external eeprom startup l, [s] from v cc >80% to first output clock edge (0 retries) at minimum i 2 c frequency 150 200 ms from v cc >80% to first output clock edge (0 retries) at maximum i 2 c frequency 130 150 ms from v cc >80% to first output clock edge (32 retries) at minimum i 2 c frequency 820 1200 ms from v cc >80% to first output clock edge (32 retries) at maximum i 2 c frequency 350 500 ms [a] v ccox denotes v cco0 , v cco1 , v cco2 , v cco3 . [b] electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after thermal equ ilibrium has been reached under these conditions. [c] appropriate se_mode bit must be configured to select phase-aligned or phase-inverted operation. [d] all q and nq outputs in phase-inverted operation. [e] this parameter is guaranteed by characterization. not tested in production. [f] this parameter is defined in accordance with jedec standard 65. [g] measured at the output differential cross point. [h] defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. [i] characterized in pll mo de. duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the d evice. [j] this parameter was measured using clk0 as the reference input and clk1 as the external feedba ck input. characterized with 8t49n240-906nlgi. [k] tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable. [l] this parameter is guaranteed by design. [m] using internal feedback mode configuration. [n] device programmed with swmode = 0 (absorbs phase differences). [o] characterized with 8t49n240-900. [p] characterized with 8t49n240-901. [q] characterized with 8t49n240-902. [r] tested with all outputs operating at 156.25mhz. [s] assuming a clear i 2 c bus. table 36. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (lvcmos logic levels only), t a = -40c to 85c [a], [b] (cont.) symbol parameter test conditions min. typ. max. units
48 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 37. hcsl ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, t a =-40c to 85c [a], [b] symbol parameter test conditions minimum typical maximum units v rb ring-back voltage margin [c], [d] -100 100 mv t stable time before v rb is allowed c, d 500 ps v max absolute max. output voltage [e], [f] 1150 mv v min absolute min. output voltage e, [g] -300 mv v cross absolute crossing voltage [h], [i] 200 500 mv ? v cross total variation of vcross over all edges h, [j] 140 mv [a] electrical parameters are guaranteed over the specified ambien t operating temperature range, which is established when the d evice is mounted in a test socket with maintai ned transverse airflow gr eater than 500 lfpm. the device will meet sp ecifications after thermal eq uilibrium has been reached under these conditions. [b] v ccox denotes v cco0 , v cco1 , v cco2 , v cco3 . [c] measurement taken from differential waveform. [d] t stable is the time the differential clock must maintain a minimum 1 50mv differential volt age after rising/fallin g edges before it is allowed to drop back into the v rb 100mv differential range. [e] measurement taken from single ended waveform. [f] defined as the maximum instantaneous voltage including overshoot. [g] defined as the minimum instantaneous voltage including undershoot. [h] measured at crossi ng point where the in stantaneous volt age value of the rising edge of qx equals the fa lling edge of nqx. [i] refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. [j] defined as the total variation of all crossing voltages of rising qx and falling nqx, this is the maximum allowed variance i n v cross for any particular system.
49 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 38. rms phase jitter, v cc = 3.3v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (lvcmos logic levels only), t a = -40c to 85c [a] [b] symbol parameter test conditions typical maximum units tjit( ? ) typical rms phase jitter (random) q0, q1, q2 f out = 122.88mhz, integration range 12khz - 20mhz jitter attenuator mode (40.8mhz crystal) [c] 199 233 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [d] 185 236 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [e] 184 237 fs q3 integer output divider f out = 122.88mhz, integration range 12khz - 20mhz; jitter attenuator mode (40.8mhz crystal) [c] 249 308 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [d] 229 270 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [e] 227 268 fs q3 fractional output divider f out = 122.88mhz, integration range 12khz - 20mhz; jitter attenuator mode (40.8mhz crystal) [f] 239 279 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [g] 243 312 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [h] 222 252 fs [a] v ccox denotes v cco0 , v cco1 , v cco2 , and v cco3 . [b] tested with all outputs running at the specified output frequency. all outputs derived from pll. [c] characterized with 8t49n240-900. [d] characterized with 8t49n240-901. [e] characterized with 8t49n240-902. [f] characterized with 8t49n240-903. [g] characterized with 8t49n240-904. [h] characterized with 8t49n240-905.
50 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 39. rms phase jitter, v cc = 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (lvcmos logic levels only), t a = -40c to 85c [a] [b] symbol parameter test conditions typical maximum units tjit( ? ) typical rms phase jitter (random) q0, q1, q2 f out = 122.88mhz, integration range 12khz - 20mhz jitter attenuator mode (40.8mhz crystal) [c] 220 299 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [d] 192 266 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [e] 205 299 fs q3 integer output divider f out = 122.88mhz, integration range 12khz - 20mhz; jitter attenuator mode (40.8mhz crystal) [c] 277 359 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [d] 243 292 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [e] 242 326 fs q3 fractional output divider f out = 122.88mhz, integration range 12khz - 20mhz; jitter attenuator mode (40.8mhz crystal) [f] 247 287 fs f out = 156.25mhz, integration range 12khz - 20mhz; jitter attenuator mode (49.152mhz crystal) [g] 251 339 fs f out = 161.1328125mhz, integration range 12khz - 20mhz; synthesizer mode (49.152mhz crystal) [h] 240 297 fs [a] v ccox denotes v cco0 , v cco1 , v cco2 , and v cco3 . [b] tested with all outputs running at the specified output frequency. all outputs derived from pll. [c] characterized with 8t49n240-900. [d] characterized with 8t49n240-901. [e] characterized with 8t49n240-902. [f] characterized with 8t49n240-903. [g] characterized with 8t49n240-904. [h] characterized with 8t49n240-905.
51 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 40. pci express jitter specifications, v cc = v ccox = 3.3v 5% or 2.5v 5%, t a = -40c to 85c [a], [b] symbol parameter test conditions min. typ. max. pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak [c], [d] ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 6.8 12 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms d,[e] ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 0.5 1.1 3.10 ps t refclk_lf_rms (pcie gen 2) phase jitter rms d, e ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.2 0.7 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms d, [f] ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.13 0.3 0.8 ps [a] v ccox denotes v cco0 , v cco1 , v cco2 , v cco3 . [b] electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is mounted in a test socket with maintai ned transverse airflow gr eater than 500 lfpm. the device will meet sp ecifications after thermal eq uilibrium has been reached under these conditions. [c] peak-to-peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci express gen 1 [d] this parameter is guaranteed by characterization. not tested in production. [e] rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture an d reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). [f] rms jitter after applying system transfer function for the common clock architecture. this specification is based on the pci express base specification revision 0.7, october 2009 and is subject to change pending the final release version of the specification.
52 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet typical phase noise at 156.25mhz
53 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet applications information recommendations for unused input and output pins inputs clkx/nclkx input for applications not requiring the use of one or more reference clock inputs, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. it is recommended that clkx, nclkx not be driven with active signals when not selected. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional prot ection. a 1k ? resistor can be used. outputs lvpecl outputs any unused lvpecl output pair can be left floating. we recommend that there is no trace attached. both sides of the differentia l output pair should either be left floating or terminated. lvds outputs any unused lvds output pair can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs any lvcmos output can be left floating if unused. there should be no trace attached. hcsl outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the different ial output pair should either be left floating or terminated.
54 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet overdriving the xtal interface the osci input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the osco pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prev ent signal interference with the power rail and to reduce internal noise. figure 6 shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in pa rallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 6. general diagram for lvcmos driver to xtal input interface figure 7 shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 7. general diagram for lvpe cl driver to xtal input interface lvcmos_driver zo = 50 rs zo = ro + rs ro r2 100 r1 100 vcc osco osci c1 0.1 f lvpecl_driver zo = 50 r2 50 r3 50 c2 0.1 f osco osci zo = 50 r1 50
55 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet wiring the differential input to accept single-ended levels figure 8 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should b e located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termin ation at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended sig naling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvc mos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only appl ies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 8. recommended schematic for wiring a differential input to accept single-ended levels
56 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet 3.3v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 9 to figure 13 show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 9 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termi nation recommendation. figure 9. cl kx/nclkx input driven by an idt open emitter lvhstl driver figure 10. clkx/nclkx input driven by a 3.3v lvpecl driver figure 11. clkx/nclkx input driven by a 3.3v lvpecl driver figure 12. clkx/nclkx input driven by a 3.3v lvds driver figure 13. clkx/nclkx input driven by a 3.3v hcsl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differenti al input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input
57 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet 2.5v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 14 to figure 18 show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the dr iver termination requirements. for example, in figure 14 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 14. clkx/nclkx input driven by an idt open emitter lvhstl driver figure 15. clkx/nclkx input driven by a 2.5v lvpecl driver figure 16. clkx/nclkx input driven by a 2.5v lvpecl driver figure 17. clkx/nclkx input driven by a 2.5v lvds driver figure 18. clkx/nclkx input driven by a 2.5v hcsl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 2.5v lvhstl idt open emitter lvhstl driver differential input hcsl *r3 33 *r4 33 clk nclk 2.5v 2.5v zo = 50 zo = 50 differential input r1 50 r2 50 *optional C r3 and r4 can be 0
58 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full lin e of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 19 can be used with either type of output structure. figure 20 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capac itor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output s tructure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 19. standard lvds termination figure 20. optional lvds termination
59 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) o r current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 21 and figure 22 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the b oard designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 21. 3.3v lvpecl output termination figure 22. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v + _
60 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet termination for 2.5v lvpecl outputs figure 23 to figure 25 show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 25 can be eliminated and the termination is shown in figure 24 . figure 23. 2.5v lvpecl driver termination example figure 24. 2.5v lvpecl driver termination example figure 25. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
61 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet hcsl recommended termination figure 26 is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 26. recommended source termination (where the driver and receiver will be on separate pcbs) figure 27 is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflec tions will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. th e optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 27. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express ad d -in c a rd pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
62 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 28 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be desi gned on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board thro ugh a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pa ttern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recomme nded to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process w hich may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solde r voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 28. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) schematic and layout information please contact idt for schematic and layout information relevant to this product. contact information can be found on the last page of this datasheet. crystal recommendation this device will be validated using fox 277lf series through-hole crystals including part # 277lf-40-18 (40mhz). if a surface m ount crystal is desired, the fox fx325bs series of crystals at an appropriate frequency, such as part # 603-30-38 (40mhz), is recomm ended for use with this product.
63 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. figure 29. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g., for a 100mhz reference clock: 0hz?50mhz) and the jitter result is reported in peak-peak. figure 30. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. figure 31. pcie gen 2a magnitude of transfer function figure 32. pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. figure 33. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note, pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
64 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet power dissipation and thermal considerations the 8t49n240 is a multi-functional, high-speed device that targets a wide variety of clock frequencies and applications. since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as these features and functions are enabled. the 8t49n240 is designed and characterized to operate within the ambient industrial temperature range of -40c to 85c. the amb ient temperature represents the temperature around the device, not the junction temperature. when using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and re liable junction temperature. extreme care must be taken to avoid exceeding a 125c junction temperature. the power calculation examples in this section are generated using maximum ambient temperature and supply voltage. for many applications, the power consumption will be much lower. for any concerns on calculating the power dissipation for your own spec ific configuration, please contact idt technical support. power domains the 8t49n240 has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). figure 34 indicates the individual domains and the associated power pins. figure 34. 8t49n240 power domains power consumption calculation the process of determining total power consumption involves the following steps: 1. determine the power consumption using maximum current values for core and analog voltage supplies from table 26 and table 27 . 2. determine the nominal power consumption of each enabled output path, which consists of: a. a base amount of power that is independent of operating frequency, as shown in table 42 to table 50 (depending on the chosen output protocol). b. a variable amount of power that is related to the output frequency. this can be determined by multiplying the output frequenc y by the fq_factor shown in table 42 to table 50 . 3. all of the above totals are summed. ? ? clk ? input ? & ? divider ? block ? ? (core ? v cc ) ? ? analog ? & ? digital ? pll ? (v cca ? & ? core ? v cc ) ? output ? divider ? / ? buffer ? q0 ? (v cco0 ) output ? divider ? / ? buffer ? q1 ? (v cco1 ) ? output ? divider ? / ? buffer ? q2 ? (v cco2 ) ? ? divider ? / ? buffer ? q3 ? (v cco3 )
65 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet thermal considerations once the total power consumption is determined, it is necessary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. thermal conduction paths, air flow rate, and ambient air temperature are factors that can affect this calculation. the thermal conduction path refers to whether heat is to be conducted away via a heatsink, via air flow, or via conduction into the pcb through the device pads (including the epad). thermal conduction data is provided for typical scenarios in table 41 . for assistance with calculating results under other scenarios, please contact idt technical support. current consumption data and equations table 41. thermal resistance ? ja for 40-lead vfqfn, forced convection ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 26.3c/w 23.2c/w 21.7c/w table 42. 3.3v lvpecl output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00642 41.9 q1 q2 q3 0.00628 47.6 table 43. 3.3v hcsl output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00567 42.0 q1 q2 q3 0.00691 47.6 table 44. 3.3v lvds output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00586 51.5 q1 q2 q3 0.00644 57.0
66 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet table 45. 2.5v lvpecl output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00290 38.6 q1 q2 q3 0.00493 43.8 table 46. 2.5v hcsl output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00257 38.7 q1 q2 q3 0.00505 43.7 table 47. 2.5v lvds output calculation output fq_factor (ma/mhz) base_current (ma) q0 0.00293 47.5 q1 q2 q3 0.00467 52.6 table 48. 3.3v lvcmos output calculation output base_current (ma) q3 43.42 table 49. 2.5v lvcmos output calculation output base_current (ma) q3 40.54
67 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet applying the values to the following equation will yield output current by frequency: qx current (ma) = fq_factor * frequency (mhz) + base_current where: qx current is the specific output current according to output type and frequency fq_factor is used for calculating current increase due to output frequency base_current is the base current for each output path independent of output frequency the second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: t j = t a + ( ? ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) ? ja is the thermal resistance value from table 41 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8t49n240 under usage conditions, including power dissipated due to loading (w). note that the power dissipation per output pair due to loading is assumed to be 27.95mw for lvpecl outputs and 44.5mw for hcsl outputs. when selecting lvcmos outputs, power dissipation through the load will vary based on a variety of factors including te rmination type and trace length. for these examples, power dissipation through loading will be calculated using c pd (found in table 26 ) and output frequency: pd out = c pd * f out * v cco 2 where: pd out is the power dissipation of the output (w) c pd is the power dissipation capacitance (f) f out is the output frequency of the selected output (hz) v cco is the voltage supplied to the appropriate output (v) table 50. 1.8v lvcmos output calculation output base_current (ma) q3 38.83
68 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet example calculations ? core supply current + control and status supply current = i cc + i cccs = 58ma (max) ? analog supply current, i cca = 186ma (max) ? output supply current: q0 current = 125 * 0.00642 + 41.9 = 42.7ma q1 current = 0ma (output disabled) q2 current = 50 * 0.00642 + 41.9 = 42.2ma q3 current = 100 * 0.00628 + 47.6 = 48.2ma ? total output supply current = 133.1ma (max) ? total device current = 58ma + 186ma + 133.1ma = 377.1ma ? total device power = 3.465v * 377.1ma = 1306.7mw ? power dissipated through output loading: lvpecl = 27.95mw * 3 = 83.85mw lvds = already accounted for in device power hcsl = n/a lvcmos = n/a ? total power = 1306.7mw + 83.85mw = 1390.6mw or 1.4w with an ambient temperature of 85c and no airflow, the junction temperature is: t j = 85c + 26.3c/w * 1.4w = 122c this is below the limit of 125c. table 51. example 1: common customer configuration (3.3v core voltage) output output type frequency (mhz) v cco q0 lvpecl 125 3.3 q1 disabled disabled 3.3 q2 lvpecl 50 3.3 q3 lvpecl 100 3.3
69 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet ? core supply current + control and status supply current = i cc + i cccs = 55ma (max) ? analog supply current, i cca = 179ma (max) ? output supply current: q0 current = 156.25 * 0.00290 + 38.6 = 39.0ma q1 current = 125 * 0.00293 + 47.5 = 47.9ma q2 current = 125 * 0.00257 + 38.7 = 39ma q3 current = 40.5ma ? total output supply current = 166.4ma (max) ? total device current = 55ma + 179ma + 166.4ma = 400.4ma ? total device power = 2.625v * 400.4ma = 1051mw ? power dissipated through output loading: lvpecl = 27.95mw * 1 = 27.95mw lvds = already accounted for in device power hcsl = 45.5mw * 1 = 44.5mw lvcmos = 15pf * 25mhz * (2.625v) 2 * 1 output pair = 2.58mw ? total power = 1051mw + 27.95mw + 44.5mw + 2.58mw = 1126mw or 1.13w with an ambient temperature of 85c and no airflow, the junction temperature is: t j = 85c + 26.3c/w * 1.13w = 114.7c this is below the limit of 125c. table 52. example 2: common customer configuration (2.5v core voltage) output output type frequency (mhz) v cco q0 lvpecl 156.25 2.5 q1 lvds 125 2.5 q2 hcsl 125 2.5 q3 lvcmos 25 2.5
70 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet ? core supply current + control and status supply current = i cc + i cccs = 55ma (max) ? analog supply current, i cca = 179ma (max) ? output supply current: q0 current = 156.25 * 0.00642 + 41.9 = 42.9ma q1 current = 156.25 * 0.00293 + 47.5 = 48.0ma q2 current = 50 * 0.00567 + 42.0 = 42.3ma q3 current = 38.8ma ? total output supply current = 85.2ma (v cco = 3.3v), 48ma (v cco = 2.5v), 38.8ma (v cco = 1.8v) total device current: 3.3v: 85.2ma 2.5v: 55ma + 179ma + 48ma = 282ma 1.8v: 38.8ma ? total device power = 3.465v * 85.2ma + 2.625v * 282ma + 1.89v * 38.8ma = 1108.8mw ? power dissipated through output loading: lvpecl = 27.95mw * 1 = 27.95mw lvds = already accounted for in device power hcsl = 45.5mw * 1 = 45.5mw lvcmos = 15pf * 33.333mhz * (1.89v) 2 * 1 output pair = 1.79mw ? total power = 1108.8mw + 27.95mw + 44.5mw + 1.79mw = 1183mw or 1.2w with an ambient temperature of 85c and no airflow, the junction temperature is: t j = 85c + 26.3c/w * 1.2w = 116.6c this is below the limit of 125c. table 53. example 3: common customer configuration (2.5v core voltage) output output type frequency (mhz) v cco q0 lvpecl 156.25 3.3 q1 lvds 156.25 2.5 q2 hcsl 50 3.3 q3 lvcmos 33.333 1.8
71 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet reliability information transistor count the transistor count for 8t49n240 is: 537,496. table 54. ? ja vs. air flow for a 40-vfqfn [a] [a] assumes 5x5 grid of solder balls under epad area for thermal condition. ? ja vs. air flow meters per second 0 1 2 multi-layer pcb, jedec standard test boards 26.3c/w 23.2c/w 21.7c/w
72 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet package drawings figure 35. 40-vfqfn package ? sheet 1
73 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet figure 36. 40-vfqfn package ? sheet 2
74 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet recommended land pattern figure 37. recommended land pattern
75 ?2017 integrated device technology, inc. may 31, 2017 8t49n240 datasheet ordering information table 55. ordering information part/order number [a] [a] for the specific -ddd order codes, refer to femtoclock ng universal frequency translator ordering product information . marking package [b] [b] for information about pin 1 orientation in tape and reel packaging, see table 56 . shipping packaging temperature 8t49n240-dddnlgi idt8t49n240nlgi 6 x 6 x 0.9 mm 40-vfqfn tray -40 ? c to +85 ? c 8T49N240-DDDNLGI8 idt8t49n240nlgi 6 x 6 x 0.9 mm 40-vfqfn, quadrant 1 tape and reel -40 ? c to +85 ? c 8t49n240-dddnlgi# idt8t49n240nlgi 6 x 6 x 0.9 mm 40-vfqfn. quadrant 2 tape and reel -40 ? c to +85 ? c table 56. pin 1 orientation in tape and reel packaging part number suffix pin 1 orientation illustration nlgi8 quadrant 1 (eia-481-c) nlgi# quadrant 2 (eia-481-d) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes)
8t49n240 datasheet 76 ?2017 integrated device technology, inc. may 31, 2017 disclaimer integrated device te chnology, inc. (idt) and its aff iliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specific ations described herein at any time, without notice, at idt?s sole discretion. performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of idt's products for any particular purpose, an implied warran ty of merchantab ility, or non-infringement of the intellectual p roperty rights of others. this documen t is presented only as a guide and does not convey any license under intellectual propert y rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com revision history revision date description of change may 31, 2017 initial release.

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